QINETIQ: MEMS processes

QinetiQ provides microsystems solutions based on 3 core MEMS process technology families :

• Polysilicon surface micromachining (PPK) : Figure 1
• Metal-nitride surface micromachining (MPK) : Figure 2
• SOI micromachining (DPK) : Figure 3

Figure 1 : Cross-section (not to scale) of the Polysilicon surface micromachining (PPK) process.

Figure 2 : Cross-section (not to scale) of the Metal-nitride surface micromachining (MPK) process.

Figure 3 : Cross-section (not to scale) of the SOI micromachining (DPK) process.

A broad range of applications have been demonstrated in these processes and low cost access services were launched as part of the INTEGRAM Europractice Framework V programme based on multi-project wafers (MPW) with limited flexibility or on single project wafers (SPW) with added flexibility.

The polysilicon surface micromachining process was originally developed in the early 1990’s and has been stable for many years whilst the need to develop monolithically integrated devices led to the development of a metal-nitride process with similar characteristics to polysilicon but capable of being post-processed on standard CMOS at low temperatures. The SOI micromachining process based on deep dry etching (or DRIE) enables high aspect ratio structures and a thicker structural layer (10-100µm) than surface micromachining processes (0.2-3µm) and also has the potential to be post-processed on standard CMOS.

Each process is supported by a design handbook containing information to enable a designer to simulate devices. This has already been encoded into CAD support files for CoventorWare™. Over the course of the project, enhancements to the processes are planned that will be reflected in updates to the design handbooks and associated support files. This includes potential extensions to offer wafer-level or chip-level packaging.

To support microsystems design services, QinetiQ uses a mixture of general CAD tools (e.g. MathCAD™ for analytical modelling and MATLAB for system-level simulation) and specific MEMS CAD tools (CoventorWare Analyzer™ for finite element analysis and Architect™ for device-level simulation). The latter are used for thermo-electro-mechancial analysis and statistical (tolerance) analysis. Additionally, QinetiQ primarily uses Tanner L-Edit™ for 2-D device layout (with design rule checking) and Orcad P-Spice™ or Architect for full microsystem (MEMS + electronics) simulation. Additionally, QinetiQ uses Cadence, Mentor and Silvaco tools as required for IC design and semiconductor device analysis.